| Page | Block | Signals to probe | |------|-------|------------------| | 3 | System block diagram | Traces power flow: DC → ALW → S5 → S0 | | 8 | SIO (ITE8987) | LID_SW#, AC_IN, PWRBTN#, RSMRST# | | 12 | SPI ROM (BIOS) | CS#, DO, DI, CLK (measure with scope on power-up) | | 18 | USB & Audio | USB_OC# (overcurrent faults cause no boot) | | 22 | PCIe & WLAN | WLAN_DISABLE# (high = enable) | | 26 | EC embedded controller | KBC_PWRBTN#, EC_RSMRST# |
The schematic is usually a PDF file containing two distinct sections: La-e791p Rev 2.0 Schematic Diagram
Also, think about the audience's needs. They might not just want a description but also insights into what the revisions improve. For example, if Rev 2.0 includes better power efficiency or enhanced signal integrity, that's worth highlighting. Address potential issues from prior versions and how they were resolved. | Page | Block | Signals to probe
Design feature: Rev 2.0 adds on each PCIe lane power pin—a direct response to noise complaints in Rev 1.0. Address potential issues from prior versions and how
Look for the dual MOSFETs or the PWM Controller chip (often a RT series chip like RT8223 or similar).
+1.2V_VDDQ ---[R1110]--- VREF_DDR (Pin 7 of U300) | GND